Directory  News Latest News |
| Problems Afoot with AMD's 65nm Process |
|
|
|
 We ran across an interesting analysis of AMD's Thermal Design Guidelines over at Investors Hub. It appears that AMD is speed binning their 65nm parts based on current leakage, indicative of there being issues with their current 65nm fabrication process. AMD seems to have also further enhanced sleep states by allowing C3 Sleep States in their desktop Brisbane parts, ostensibly to lower idle current draw. On the surface it appears that AMD's still a little wet behind the ears with 65nm, something Intel's mastered for quite some time now. Investors Hub reports... I was looking through AMD's thermal design guide, and found some interesting results: If you look at the IDD current of their C1 states, you get an idea of the leakage at various voltages. I looked at their current CZ (F3 stepping, 90nm) and their DD (G0 stepping, 65nm) parts at the max P-state (1.2-1.3V for 65W TDP parts and 1.3-1.35V for 89W TDP parts) and min P-state (1.1V for all products). I pay special attention to their 3800+ part, which was their downbinned part for 90nm (therefore, highest leakage), and their higher bin parts, which presumably require binning for low leakage in order to fit in the power envelopes. Note that with the new price cuts, AMD's new 90nm downbin is a 4200+ part, which is not listed in this already outdated thermal guide. For 65nm, their downbinned part was the 3600+ part. Today, it is 4000+. Note that you can see the part name in the ID Tag. Add this page to your favorite Social Bookmarking websites           
Powered by !JoomlaComment 3.12 Copyright (C) 2007 Alain Georgette / Copyright (C) 2006 Frantisek Hliva. All rights reserved. |
||||||