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Samsung Develops Fastest GDDR5 Chips PDF Print E-mail

Author: Chris Hunter

thumb_samsunggddr5800.jpgSamsung has been tooting their horn lately with their TB drives and SSDs. They are yet again claiming another crown with their new incarnation of GDDR5. Samsung states in a press release that

 "...it has developed the world's fastest memory, a GDDR5 (series five, graphics double-data-rate memory) chip that can transfer data at six gigabits per second..."

Graphics memory is used in almost all computing platforms to move massive amounts of data related to video and generated imagery.

Samsung is releasing the ram at a density of 512Mb in a 32x16Mb, 60nm, 32bit chip array. This arrangement allows graphics data transfer rates of 24GB/s and it is 4GB/s faster that the competition. Hynix and Qimonda both have offerings of GDDR5 with a bandwidth of 20GB/s. GDDR4 sits 8GB/s lower at 16GB/. The chips run at 1.5 Volts similar to the competition, which is ~20% less power consumption than predominant GDDR3 chips of today.

GDDR5 samples were shipped to major graphics processor companies last month and mass production is anticipated H1 2008. What video cards will utilize the technology is yet to be known. However, Samsung expects the ram to become the "de facto" in high performance systems by 2010 and predicts a 50% market share.  The press release states H1 2007 for mass production. Samsung confirmed this was a typo and it is H1 2008 instead.*
The International Solid State Circuits Conference has taken notice and is selecting Samsung's technology to showcase GDDR5. The presentation will be in February of of 2008.
 
The advanced program of the ISSCC 2008 states

"A 6Gb/s/pin 32b parallel 512Mb GDDR5 SDRAM is implemented using a 60nm DRAM

process. To reduce ISI and SSN, an output data coding scheme, which includes data

bus inversion, scrambling and a data preamble, is employed, increasing the eye width

by 32ps at 6Gb/s. A fast-feedback DFE receiver with minimum overhead is also used.

An adjustable clocking scheme with PLL on/off selection is implemented. The PLL has

a programmable bandwidth, a replica delay and a locking cycle to minimize jitter."
thumb_samsunggddr5isscc.jpg

It will be interesting to see what kind of performance next generation cards hold in store for us.



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