The Pentium Pro (also known as the P6) architecture was introduced in 1995 and was the architecture that largely carried Intel into the new millennium. Even today's new Core2 architecture can trace its ancestry to the first 150 MHz Socket8 Pentium Pro's. Starting at 150 MHz, the P6 architecture scaled all the way to 1.4 GHz with the Tualatin core, and in between with many other Pentium II, Pentium III, and Celeron variants. The Pentium Pro was a very fast CPU for its day, and a very expensive one. Working at clock speeds from 150-200 MHz, the Pentium Pro had an integrated on-package (but not on-die) Level 2 cache which operated not only at the core's clock speed but also had it's own backside bus that allowed concurrent accesses to both cache and main system memory.

After the Pentium Pro came the introduction of the Pentium II available in a Slot 1 package, which housed on board L2 cache that operated at one half the core clock speed. This variant operated at frequencies from 233-300 MHz in its Klamath iteration and 333-400 MHz in the later Deschutes version. It is here where we also saw the birth of low- or no-cache variants of the Pentium II known as Intel Celeron CPUs. Also, a new Xeon server variant became available that utilized a different package known as Slot 2 and offered full-speed L2 cache on-board in quantities ranging from 512 KB to 2 MB.

1999 saw the introduction of the Pentium III. The first iteration, the Katmai, wasn't a huge improvement over the prior Pentium II. The primary differentiation was a more efficient L1 cache controller and Intel's new SSE instruction unit which was an evolutionary step past the previously-released MMX extensions. The Katmai was available in speeds from 450-600 MHz, but was soon supplanted by the Coppermine cores.

Featuring 256 KB of on-die L2 cache and significant changes to the instruction pipelines, the Coppermine boasted nearly a 30% clock-for-clock performance gain over the Katmai. Additionally, the Coppermine range scaled through a wide range of clock speeds, from 500 MHz to 1.13 GHz. By this time the Celeron concept was going strong, and Intel released variants of the Coppermine with reduced levels of cache under this name.

In what became a somewhat embarrassing event for Intel, the 1.13 GHz Coppermine was eventually recalled as a result of collaborative testing by HardOCP and Tom's Hardware in 2000. This testing pointed out fundamental instabilities in the Coppermine CPU at that clock rate. The CPU was eventually re-released in 2001 with 1.1 and 1.13 GHz variants and proven stability.

One Coppermine design based on the Mobile Celeron 733 even saw the light of day in Microsoft's XBOX console design. Another model known as the Coppermine-T never saw the light of day at all. The final Pentium III processor featured a new core, the Tualatin. This CPU was developed primarily for the workstation and small server market and was a trial-run for Intel's new 0.13 micron manufacturing process. The smaller process allowed the Pentium III to scale from 1.0 GHz to 1.4 Ghz. Although the Tualatin could have probably gone even faster, Intel deliberately didn't increase the clock speeds beyond 1.4 GHz so as not to erode the potential for it's new architecture, the Pentium 4.

The release of the Pentium 4 saw a fork in Intel's x86 CPU development. The Pentium 4 was an entirely new 7th generation architecture known as the P7, but P6-derived architectures were still being developed for mobile processors at the aforementioned Haifa, Israel research center.

The P7 architecture, known as NetBurst, was basically a ground-up redesign of their architecture relative to the P6. The key features of the P7 microarchitecture are it's very deep pipeline stages meant to foster rapid increases in clock rate, advanced in SSE instruction sets including SSE2 and SSE3, and it's implementation of a Quad Data Rate bus, whereby 4 bits of information can be transferred within the rise and fall of a single clock period. These changes allowed the Pentium 4 over it's lifespan to scale in clock speed at rates never before seen. Moreover, the utilization of a Quad Data Rate bus allowed them to do so while mitigating the potential memory bandwidth issues when running system memory at much lower clock rates than the CPU core.

More processors were released under the Pentium 4 branding than any previous x86 iteration. The first variant to be released used the Willamette core that ranged from 1.3 GHz to 2.0 GHz. It's interesting to note that not only did the Willamette under-perform clock for clock relative to the Pentium III/Tualatin cores, it also faired worse than AMD's Athlon line.

Intel eventually gained some ground against AMD in with the release of the Northwood core. These CPUs ranged in clock speeds from 1.6 GHz all the way to 3.4 GHz, in multiple front-side-bus (FSB) variants. The Northwood FSBs operated at 100 MHz (400 MHz QDR), 133 Mhz (533 MHz QDR), and 200 MHz (800 MHz QDR). Later Northwood CPUs also brought a new feature called Hyperthreading to the Intel line. Hyperthreading allows a single core to present itself as two virtual processors to an operating system, and helped the P4 architecture to operate more efficiently under multitasking situations while putting it's very deep pipelines to somewhat better use.

Despite continual enhancements to the Pentium 4 line, Intel still lagged AMD. At the same time, Intel's own mobile Pentium M CPUs based on the older P6 architecture managed to outperform the Pentium 4 in productivity application benchmarks. In an attempt to turn away the AMD attack mounting at its front gate, Intel pressed the Xeon's Gallatin core into service as the Pentium 4 Extreme Edition. This CPU was fast and boasted a generous 2 MB of Level 3 cache, but its detractors were quick to dub it the “Pentium 4 Emergency Edition”. While the additional L3 cache did bring significant improvements in applications such as media encoding, the extremely-pricey P4EE did little to improve the image of the Pentium 4 line. Indeed, in some minor areas, the P4EE could even be slightly slower than similarly clocked Northwoods due to increased latencies associated with the large L3 cache.

Intel continued to try and help its marketing with even higher clock speeds with the release of Prescott, its final NetBurst core. The Prescott CPUs deepened the P4's pipeline stages even further in an attempt to continue the architecture's stellar ability to scale in clock speed, but massive thermal and electrical barriers manifested. The Prescott was even slower than comparably-clocked Northwoods, and despite intended improvements in electrical energy consumption these CPUs used about 10% more power per clock as well.

Seeing the writing on the wall, Intel finally decided to take its desktop line in a new direction. Before finally doing so however, a few additions were made to the Pentium 4 line that saw the adoption of the EMT64 instruction set and a much larger L2 cache. As with the Pentium III before it, the final Pentium 4 variants took advantage of Intel's latest manufacturing process to eke the last bit of performance from the architecture.